Developments of semiconductor memory devices have been generally concentrated on chip miniaturization, high speed, high integration, and the like, resulting in the recent advent of high performance products. The higher the performance of products is, the more seriously the developments should be carried out while considering possible noises. Specifically, for example, if a large peak current is used to speed up the operation, a quick change in current will generate power source noises. As a means for suppressing such noises, there is widely used a method of supplying power to an internal circuit and an output circuit independently from different power sources. Power source noises do not always generate regularly. For example, in a multi-port memory, each port operates asynchronously, so that power source noises are generated at an irregular period. A device which generates irregular noises due to asynchronous circuit operation produces sometimes an erroneous data output because it happens that noises are superposed one upon another. Accordingly, it is not sufficient for a multi-port memory or the like to provide independent power sources, requiring another means for suppressing noises.
An erroneous operation caused by a superposition of noises will be described taking as an example a semiconductor memory device having two independent power sources and operating asynchronously such as in the case of a multi-port memory.
FIG. 1 shows such a conventional semiconductor memory device wherein the data output circuit in particular is shown in detail and one of a plurality of ports is shown. In FIG. 1, a memory cell array 4 of an internal circuit 10 has a plurality of memory cells disposed in a matrix. In this array 4, a row address Al and column address A2 are decoded by decoders 5 to select a particular memory cell. Complementary data D and D of the selected memory cell is applied to an output control circuit 3 which operates to read data from the memory cell array 4. The output control circuit 3 may take various circuit arrangements one example of which is shown in FIG. 2. In this circuit, data D and D is inputted to two AND gates I and II, and an enable signal is applied to an enable terminal ENBL. This output control circuit 3 has first and second output nodes. The first node 1 is connected to the gate of an N-channel transistor T1 of an output circuit 20, and the second node 2 is connected to the gate of another N-channel transistor T0. The interconnection between the transistors T1 and T0 is used as a data output terminal D.sub.out. Power is supplied to the semiconductor memory cell array 4 and output control circuit 3 from a power source P1 (V.sub.cc1, V.sub.ss1) dedicated to the internal circuit. Power is supplied to the transistors T1 and T0 from another power source P.sub.2 (V.sub.cc2, V.sub.ss2) dedicated to the output circuit 20 different from the power source P1 dedicated to the internal circuit. Other ports are constructed having similar internal circuits 10 and output circuits 20.
With the circuit arrangement described above, data stored in the memory cell array 4 is read from the output control circuit 3. The read-out data controls the gates of the transistors T1 and T0 via the first and second nodes 1 and 2, and is outputted from the data output terminal D.sub.out.
Consider now that an output from the data output terminal D.sub.out fully swings from "1" to "0". If an output at the data output terminal D.sub.out is "1", the first node 1 has the power source voltage V.sub.cc1, and the second node 2 has the ground potential V.sub.ss1. Therefore, the transistor T1 turns on and the transistor T0 turns off. If the output at the data output terminal D.sub.out is to be changed to "0", the levels at the nodes 1 and 2 of the output control circuit 3 are exchanged. Namely, the first node 1 has the ground potential V.sub.ss1, and the second node 2 has the power source voltage V.sub.cc1. As a result, the transistor T1 turns off and at the same time the transistor T0 turns on to output "0" from the data output terminal D.sub.out.
There will be described with reference to the equivalent circuit shown in FIG. 3 the potential change of the ground potentials V.sub.ss1 and V.sub.ss2 when the transistor TO turns on and the level at the data output terminal D.sub.out changes from "1" to "0".
As seen from FIG. 3, the internal circuit 10 has a pad Pad 1 for the ground potential V.sub.ss1. The output circuit 20 has a pad Pad 2 for the ground potential V.sub.ss2. It can be considered that a resistance R of wirings or the like is present between the pad Pad 2 and the transistor T0. Between the pad Pad 2 and the external absolute ground, there is present an inductance L of inner leads, wirings, or the like. An external load 30 is connected to the output circuit 20. This external load 30 can be considered as having a large capacitance such as 100 pF. Therefore, this capacitance CL is charged sufficiently as shown in FIG. 3. Thereafter, as the transistor T1 turns off and the transistor T0 turns on to change the level at the data output terminal D.sub.out to "0", a discharge circuit DC is formed as indicated by a two-dot chain line shown in FIG. 3. The electric charge in the capacitor CL is discharged via the discharge circuit DC. However, as described above, the discharge circuit DC includes the resistor R and inductor L so that the capacitor repeats charge/discharge operations in alternate directions. That is, the potential at the data output terminal D.sub.out oscillates as shown in FIG. 4(a). Apart from the above, the device shown in FIG. 1 is constructed as a multi-port memory wherein the ports shown in FIG. 1 and other ports not shown operate asynchronously, i.e., independently. It is assumed that a sense amplifier of the internal circuit 10 operates for the ports not shown, and that considerable power source noises are generated. In such a case, as shown in FIG. 4(b), the ground potential V.sub.ss1 of the power source P1 dedicated to the internal circuit will rise. If this rise of the ground potential V.sub.ss1 and the fall of the level at the data output terminal D.sub.out described above take a phase relationship as shown in FIG. 4(b), a large potential difference will be generated between a pair of ground potentials V.sub.ss1 and V.sub. ss2. The influence of this potential difference causes the potential V.sub.ss2 at the data output terminal D.sub.out to further rise as it oscillates in the manner described above. As a result, an output which should be "0" does not become "0" and is considered as "1", leading to an error of a low level output voltage V.sub.OL.